IBM has unveiled what it says is the world’s first sub-1 nanometre (nm) chip technology, introducing an experimental 0.7nm semiconductor built around a new three-dimensional transistor architecture called nanostack.
The company said the research chip packs nearly 100 billion transistors onto a chip roughly the size of a fingernail, almost twice the transistor density of its 2nm chip announced in 2021, and demonstrates a path to extending Moore’s Law beyond current manufacturing limits.
According to IBM, the new chip could deliver up to 50% higher performance or 70% greater energy efficiency than its 2nm technology, depending on operating conditions.
The company said the technology is intended for future AI infrastructure, cloud computing systems and next-generation electronic devices, though commercial deployment is not expected for at least five years.
The breakthrough centres on IBM’s new nanostack architecture, which vertically stacks and staggers nanosheet transistors instead of arranging them solely in a two-dimensional layout.
The design uses sequential 3D integration to increase transistor density while allowing different semiconductor materials in each stacked layer, enabling engineers to optimise performance and power characteristics independently.
“This industry-first innovation continues IBM’s legacy of leading in next-generation technologies and sets the foundation for the next era of computing,” says Jay Gambetta, Director of IBM Research and IBM Fellow.
IBM said researchers experimentally validated the architecture through ultra-thin dielectric bonding, dual-channel engineering and functional CMOS inverter operation, demonstrating that the stacked design can perform logic operations.
Separately, research presented at the VLSI 2026 conference showed the nanostack approach achieving 40% SRAM scaling, which IBM said could help improve memory density and bandwidth for AI workloads.
The company said the technology represents the first logic platform to extend below the 1nm process node into the angstrom era.
While process node names no longer correspond directly to physical transistor dimensions, IBM said the 0.7nm node demonstrates that further scaling remains feasible despite the industry’s increasing physical constraints.
IBM continues to develop the technology through its semiconductor research centre in Albany, New York, alongside partners including ASML, Lam Research, Tokyo Electron and SCREEN Semiconductor Solutions.
The facility is expected to house a High Numerical Aperture Extreme Ultraviolet (High NA EUV) lithography system, which IBM said will support future generations of advanced chip manufacturing.
The announcement builds on IBM’s long-running semiconductor research programme, which produced the industry’s first 2nm chip prototype in 2021.
The company conducts much of its semiconductor R&D at its Albany, New York, research facility, where it is working with partners including Lam Research, Tokyo Electron and SCREEN Semiconductor Solutions to develop High Numerical Aperture Extreme Ultraviolet (High-NA EUV) lithography processes and tools for future logic scaling.
The site is also set to house an ASML High-NA EUV lithography system, designed to print increasingly smaller and denser circuits.
Earlier this year, IBM and Lam Research expanded their partnership through a five-year agreement to develop materials, fabrication processes and High-NA EUV technologies for sub-1nm logic, building on more than a decade of collaboration spanning 7nm, nanosheet and 2nm semiconductor research.
Although IBM exited commercial chip manufacturing after selling its fabrication business to GlobalFoundries in 2015, it continues to develop next-generation semiconductor technologies through research partnerships that can later be adopted by foundries.
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